Traditionally, CMOS fabrication has been divided into digital and analog device fabrication techniques. Known electronic devices employ separate digital and analog chips having different (i) substrate, (ii) voltage, (iii) frequency, and (iv) fabrication requirements, all of which increase chip real estate demands and fabrication complexity.
Reducing the supply voltage of high performance FETs is a known effective approach for power scaling. In addition, silicon (Si)-based CMOS technologies require gate-architecture changes to suppress the short-channel effect and OFF-state leakage current. Further, using different channel materials is known to enhance the ON-state current at a lower electrical field and, therefore, enable lower power consumption.
A need therefore exists for methodology enabling fabrication of integrated digital and analog circuits on a single substrate that is scalable and compatible with current integrated circuit (IC) fabrication technology, and the resulting device.